R8CSLASH29 datasheet(289/471 Pages) RENESAS

289 / 471 page

R8C/28 Group, R8C/29 Group

16. Clock Synchronous Serial Interface

Rev.2.10

Sep 26, 2008

Page 272 of 441

REJ09B0279-0210

16.2.6

Operation in 4-Wire Bus Communication Mode

In 4-wire bus communication mode, a 4-wire bus consisting of a clock line, a data input line, a data output line,

and a chip select line is used for communication. This mode includes bidirectional mode in which the data input

line and data output line function as a single pin.

The data input line and output line change according to the settings of the MSS bit in the SSCRH register and

the BIDE bit in the SSMR2 register. For details, refer to 16.2.2.1 Association between Data I/O Pins and SS

Shift Register. In this mode, clock polarity, phase, and data settings are performed by bits CPOS and CPHS in

the SSMR register. For details, refer to 16.2.1.1 Association between Transfer Clock Polarity, Phase, and

Data.

When this MCU is set as the master device, the chip select line controls output. When clock synchronous serial

I/O with chip select is set as a slave device, the chip select line controls input. When it is set as the master

device, the chip select line controls output of the SCS pin or controls output of a general port according to the

setting of the CSS1 bit in the SSMR2 register. When the MCU is set as a slave device, the chip select line sets

the SCS pin as an input pin by setting bits CSS1 and CSS0 in the SSMR2 register to 01b.

In 4-wire bus communication mode, the MLS bit in the SSMR register is set to 0 and communication is

performed MSB-first.

16.2.6.1

Initialization in 4-Wire Bus Communication Mode

Figure 16.18 shows the Initialization in 4-Wire Bus Communication Mode. Before the data transit/receive

operation, set the TE bit in the SSER register to 0 (transmit disabled), the RE bit in the SSER register to 0

(receive disabled), and initialize the clock synchronous serial I/O with chip select.

To change the communication mode or format, set the TE bit to 0 and the RE bit to 0 before making the change.

Setting the RE bit to 0 does not change the settings of flags RDRF and ORER or the contents of the SSRDR

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