R8CSLASH29 datasheet(293/471 Pages) RENESAS

293 / 471 page

R8C/28 Group, R8C/29 Group

16. Clock Synchronous Serial Interface

Rev.2.10

Sep 26, 2008

Page 276 of 441

REJ09B0279-0210

16.2.6.3

Data Reception

Figure 16.20 shows an Example of Clock Synchronous Serial I/O with Chip Select Operation during Data

Reception (4-Wire Bus Communication Mode). During data reception, clock synchronous serial I/O with chip

select operates as described below.

When the MCU is set as the master device, it outputs a synchronous clock and inputs data. When the MCU is

set as a slave device, it outputs data synchronized with the input clock while the SCS pin receives “L” input.

When the MCU is set as the master device, it outputs a receive clock and starts receiving by performing a

dummy read of the SSRDR register.

After 8 bits of data are received, the RDRF bit in the SSSR register is set to 1 (data in the SSRDR register) and

receive data is stored in the SSRDR register. When the RIE bit in the SSER register is set to 1 (RXI and OEI

interrupt requests enabled), an RXI interrupt request is generated. When the SSRDR register is read, the RDRF

bit is automatically set to 0 (no data in the SSRDR register).

Read the receive data after setting the RSSTP bit in the SSCRH register to 1 (after receiving 1-byte data, the

receive operation is completed). Clock synchronous serial I/O with chip select outputs a clock for receiving 8

bits of data and stops. After that, set the RE bit in the SSER register to 0 (receive disabled) and the RSSTP bit to

0 (receive operation is continued after receiving 1-byte data) and read the receive data. When the SSRDR

When the 8th clock rises while the RDRF bit is set to 1, the ORER bit in the SSSR register is set to 1 (overrun

error: OEI) and the operation is stopped. When the ORER bit is set to 1, reception cannot be performed.

Confirm that the ORER bit is set to 0 before restarting reception.

The timing with which bits RDRF and ORER are set to 1 varies depending on the setting of the CPHS bit in the

SSMR register. Figure 16.20 shows when bits RDRF and ORER are set to 1.

When the CPHS bit is set to 1 (data download at the odd edges), bits RDRF and ORER are set to 1 at some

point during the frame.

The sample flowchart is the same as that for the clock synchronous communication mode (refer to Figure 16.16

Sample Flowchart of Data Reception (MSS = 1) (Clock Synchronous Communication Mode)).

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