R8CSLASH29 datasheet(297/471 Pages) RENESAS

297 / 471 page

R8C/28 Group, R8C/29 Group

16. Clock Synchronous Serial Interface

Rev.2.10

Sep 26, 2008

Page 280 of 441

REJ09B0279-0210

16.3

I2C bus Interface

The I2C bus interface is the circuit that performs serial communication based on the data transfer format of the

Philips I2C bus.

Table 16.5 lists the Specifications of I2C bus Interface, Figure 16.22 shows a Block Diagram of I2C bus Interface,

and Figure 16.23 shows the External Circuit Connection Example of Pins SCL and SDA. Figures 16.24 to 16.30

show the registers associated with the I2C bus interface.

* I2C bus is a trademark of Koninklijke Philips Electronics N. V.

NOTE:

1. All sources use one interrupt vector for I2C bus interface.

Table 16.5

Specifications of I2C bus Interface

Item

Specification

Communication formats •I2C bus format

- Selectable as master/slave device

- Continuous transmit/receive operation (because the shift register, transmit

data register, and receive data register are independent)

- Start/stop conditions are automatically generated in master mode

- Automatic loading of acknowledge bit during transmission

- Bit synchronization/wait function (In master mode, the state of the SCL

signal is monitored per bit and the timing is synchronized automatically. If

the transfer is not possible yet, the SCL signal goes “L” and the interface

stands by.)

- Support for direct drive of pins SCL and SDA (N-channel open drain output)

• Clock synchronous serial format

- Continuous transmit/receive operation (because the shift register, transmit

data register, and receive data register are independent)

I/O pins

SCL (I/O): Serial clock I/O pin

SDA (I/O): Serial data I/O pin

Transfer clocks

• When the MST bit in the ICCR1 register is set to 0

The external clock (input from the SCL pin)

• When the MST bit in the ICCR1 register is set to 1

The internal clock selected by bits CKS0 to CKS3 in the ICCR1 register

(output from the SCL pin)

Receive error detection

• Overrun error detection (clock synchronous serial format)

Indicates an overrun error during reception. When the last bit of the next data

item is received while the RDRF bit in the ICSR register is set to 1 (data in the

ICDRR register), the AL bit is set to 1.

Interrupt sources

•I2C bus format ................................ 6 sources(1)

Transmit data empty (including when slave address matches), transmit ends,

receive data full (including when slave address matches), arbitration lost,

NACK detection, and stop condition detection.

• Clock synchronous serial format .... 4 sources(1)

Transmit data empty, transmit ends, receive data full and overrun error

Select functions

•I2C bus format

- Selectable output level for acknowledge signal during reception

• Clock synchronous serial format

- MSB-first or LSB-first selectable as data transfer direction

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