R8CSLASH29 datasheet(45/471 Pages) RENESAS

45 / 471 page

R8C/28 Group, R8C/29 Group

5. Resets

Rev.2.10

Sep 26, 2008

Page 28 of 441

REJ09B0279-0210

5.2

Power-On Reset Function

When the RESET pin is connected to the VCC pin via a pull-up resistor, and the VCC pin voltage level rises while

the rise gradient is trth or more, the power-on reset function is enabled and the MCU resets its pins, CPU, and SFR.

When a capacitor is connected to the RESET pin, too, always keep the voltage to the RESET pin 0.8VCC or more.

When the input voltage to the VCC pin reaches the Vdet0 (Vdet1 for J, K version) level or above, the low-speed

on-chip oscillator clock starts counting. When the low-speed on-chip oscillator clock count reaches 32, the internal

reset signal is held “H” and the MCU enters the reset sequence (refer to Figure 5.4). The low-speed on-chip

oscillator clock divided by 8 is automatically selected as the CPU clock after reset.

Refer to 4. Special Function Registers (SFRs) for the states of the SFR after power-on reset.

The voltage monitor 0 reset is enabled after power-on reset.

Figures 5.8 and 5.9 show the Example of Power-On Reset Circuit and Operation.

Figure 5.8

Example of Power-On Reset Circuit and Operation (N, D version)

RESET

VCC

4.7 k

Ω

(reference)

NOTES:

1. When using the voltage monitor 0 digital filter, ensure that the voltage is within the MCU operation voltage

range (2.2 V or above) during the sampling time.

2. The sampling clock can be selected. Refer to 6. Voltage Detection Circuit for details.

3. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit. Refer to 6. Voltage Detection

Circuit for details.

4. Refer to 20. Electrical Characteristics.

5. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVD0ON bit in the OFS

VCA2 register to 1.

Vdet0(3)

Vpor1

Internal

reset signal

(“L” valid)

tw(por1)

Sampling time(1, 2)

Vdet0(3)

fOCO-S

× 32

fOCO-S

× 32

Vpor2

2.2 V

External

Power VCC

trth

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