R8CSLASH29 datasheet(291/471 Pages) RENESAS

291 / 471 page

R8C/28 Group, R8C/29 Group

16. Clock Synchronous Serial Interface

Rev.2.10

Sep 26, 2008

Page 274 of 441

REJ09B0279-0210

16.2.6.2

Data Transmission

Figure 16.19 shows an Example of Clock Synchronous Serial I/O with Chip Select Operation during Data

Transmission (4-Wire Bus Communication Mode). During the data transmit operation, clock synchronous

serial I/O with chip select operates as described below.

When the MCU is set as the master device, it outputs a synchronous clock and data. When the MCU is set as a

slave device, it outputs data in synchronization with the input clock while the SCS pin is “L”.

When the transmit data is written to the SSTDR register after setting the TE bit to 1 (transmit enabled), the

TDRE bit is automatically set to 0 (data has not been transferred from registers SSTDR to SSTRSR) and the

data is transferred from registers SSTDR to SSTRSR. After the TDRE bit is set to 1 (data is transferred from

registers SSTDR to SSTRSR), transmission starts. When the TIE bit in the SSER register is set to 1, a TXI

interrupt request is generated.

After 1 frame of data is transferred while the TDRE bit is set to 0, the data is transferred from registers SSTDR

to SSTRSR and transmission of the next frame is started. If the 8th bit is transmitted while TDRE is set to 1,

TEND in the SSSR register is set to 1 (when the last bit of the transmit data is transmitted, the TDRE bit is set

to 1) and the state is retained. If the TEIE bit in the SSER register is set to 1 (transmit-end interrupt requests

enabled), a TEI interrupt request is generated. The SSCK pin remains “H” after transmit-end and the SCS pin is

held “H”. When transmitting continuously while the SCS pin is held “L”, write the next transmit data to the

SSTDR register before transmitting the 8th bit.

Transmission cannot be performed while the ORER bit in the SSSR register is set to 1 (overrun error). Confirm

that the ORER bit is set to 0 before transmission.

In contrast to the clock synchronous communication mode, the SSO pin is placed in high-impedance state while

the SCS pin is placed in high-impedance state when operating as a master device and the SSI pin is placed in

high-impedance state while the SCS pin is placed in “H” input state when operating as a slave device.

The sample flowchart is the same as that for the clock synchronous communication mode (refer to Figure 16.14

Sample Flowchart of Data Transmission (Clock Synchronous Communication Mode)).

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