R8CSLASH29 datasheet(283/471 Pages) RENESAS

283 / 471 page

R8C/28 Group, R8C/29 Group

16. Clock Synchronous Serial Interface

Rev.2.10

Sep 26, 2008

Page 266 of 441

REJ09B0279-0210

16.2.5.2

Data Transmission

Figure 16.13 shows an Example of Clock Synchronous Serial I/O with Chip Select Operation for Data

Transmission (Clock Synchronous Communication Mode). During data transmission, clock synchronous serial

I/O with chip select operates as described below.

When clock synchronous serial I/O with chip select is set as a master device, it outputs a synchronous clock and

data. When clock synchronous serial I/O with chip select is set as a slave device, it outputs data synchronized

with the input clock.

When the TE bit is set to 1 (transmit enabled) before writing the transmit data to the SSTDR register, the TDRE

bit is automatically set to 0 (data not transferred from registers SSTDR to SSTRSR) and the data is transferred

from registers SSTDR to SSTRSR.

After the TDRE bit is set to 1 (data transferred from registers SSTDR to SSTRSR), transmission starts. When

the TIE bit in the SSER register is set to 1, the TXI interrupt request is generated. When one frame of data is

transferred while the TDRE bit is set to 0, data is transferred from registers SSTDR to SSTRSR and

transmission of the next frame is started. If the 8th bit is transmitted while the TDRE bit is set to 1, the TEND

bit in the SSSR register is set to 1 (the TDRE bit is set to 1 when the last bit of the transmit data is transmitted)

and the state is retained. The TEI interrupt request is generated when the TEIE bit in the SSER register is set to

1 (transmit-end interrupt request enabled). The SSCK pin is fixed “H” after transmit-end.

Transmission cannot be performed while the ORER bit in the SSSR register is set to 1 (overrun error). Confirm

that the ORER bit is set to 0 before transmission.

Figure 16.14 shows a Sample Flowchart of Data Transmission (Clock Synchronous Communication Mode).

Figure 16.13

Example of Clock Synchronous Serial I/O with Chip Select Operation for Data

Transmission (Clock Synchronous Communication Mode)

SSCK

SSO

• SSUMS = 0 (clock synchronous communication mode), CPHS = 0 (data change at

odd numbers), and CPOS = 0 (“H” when clock stops)

1 frame

TDRE bit in

SSSR register

TEND bit in

SSSR register

TEI interrupt request

generation

Write data to SSTDR register

Processing

by program

1 frame

TXI interrupt request generation

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