R8CSLASH29 datasheet(271/471 Pages) RENESAS

271 / 471 page

R8C/28 Group, R8C/29 Group

16. Clock Synchronous Serial Interface

Rev.2.10

Sep 26, 2008

Page 254 of 441

REJ09B0279-0210

Figure 16.4

SSMR Register

SS Mode Register

Symbol

Address

After Reset

SSMR

00BAh

00011000b

Bit Symbol

Bit Name

Function

Reserved bit

NOTE:

MSB first/LSB first select bit

MLS

Nothing is assigned. If necessary, set to 0.

When read, the content is 1.

—

(b3)

—

(b4)

CPHS

CPOS

SSCK clock polarity select bit(1)

b7 b6 b5 b4 b3 b2 b1 b0

Refer to 16.2.1.1 Association betw een Transfer Clock Polarity, Phase, and Data for the settings of the CPHS

and CPOS bits.

BC1

BC2

Bits counter 2 to 0

b2 b1 b0

0 0 0 : 8 bits left

0 0 1 : 1 bit left

0 1 0 : 2 bits left

0 1 1 : 3 bits left

1 0 0 : 4 bits left

1 0 1 : 5 bits left

1 1 0 : 6 bits left

1 1 1 : 7 bits left

BC0

SSCK clock phase select bit(1)

0 : “H” w hen clock stops

1 : “L” w hen clock stops

Set to 1.

When read, the content is 1.

—

0 : Transfers data MSB first

1 : Transfers data LSB first

0 : Change data at odd edge

(Dow nload data at even edge)

1 : Change data at even edge

(Dow nload data at odd edge)

R8C/29 Datasheet(PDF) 271 Page - Renesas Technology Corp

R8C/29 Datasheet(HTML) 271 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL