R8CSLASH29 datasheet(273/471 Pages) RENESAS

273 / 471 page

R8C/28 Group, R8C/29 Group

16. Clock Synchronous Serial Interface

Rev.2.10

Sep 26, 2008

Page 256 of 441

REJ09B0279-0210

Figure 16.6

SSSR Register

SS Status Register

(7)

Symbol

Address

After Reset

SSSR

00BCh

00h

Bit Symbol

Bit Name

Function

NOTES:

7. When accessing the SSSR register continuously, insert one or more NOP instructions betw een the instructions to

access it.

SSCRH register is set to 0 (operates as slave device) and the SCS

_____

pin input changes the level from “L” to “H” during

transfer, the CE bit is set to 1.

When the serial communication is started w hile the SSUMS bit in the SSMR2 register is set to 1 (four-w ire bus

communication mode) and the MSS bit in the SSCRH register is set to 1 (operates as master device), the CE bit is set

to 1 if “L” is applied to the SCS

_____

pin input. Refer to 16.2.7 SCS

_____

Pin Control and Arbitration for more information.

When the SSUMS bit in the SSMR2 register is set to 1 (four-w ire bus communication mode), the MSS bit in the

Indicates w hen overrun errors occur and receive completes by error reception. If the next serial data receive

operation is completed w hile the RDRF bit is set to 1 (data in the SSRDR register), the ORER bit is set to 1. After the

ORER bit is set to 1 (overrun error), transmit and receive operations are disabled w hile the bit remains 1.

The TDRE bit is set to 1 w hen the TE bit in the SSER register is set to 1 (transmit enabled).

Bits TEND and TDRE are set to 0 w hen w riting data to the SSTDR register.

The RDRF bit is set to 0 w hen reading out the data from the SSRDR register.

TEND

Transmit end(1, 5)

0 : The TDRE bit is set to 0 w hen transmitting

the last bit of transmit data

1 : The TDRE bit is set to 1 w hen transmitting

the last bit of transmit data

0 : No data in SSRDR register

1 : Data in SSRDR register

Receive data register full

(1,4)

—

(b4-b3)

Conflict error flag(1)

0 : No conflict errors generated

1 : Conflict errors generated(2)

Nothing is assigned. If necessary, set to 0.

When read, the content is 0.

0 : No overrun errors generated

1 : Overrun errors generated(3)

Nothing is assigned. If necessary, set to 0.

When read, the content is 0.

—

Overrun error flag(1)

—

b7 b6 b5 b4

TDRE

Transmit data empty(1, 5, 6)

0 : Data is not transferred from registers SSTDR to

SSTRSR

1 : Data is transferred from registers SSTDR to

SSTRSR

RDRF

—

(b1)

Writing 1 to CE, ORER, RDRF, TEND, or TDRE bits invalid. To set any of these bits to 0, first read 1 then w rite 0.

b3 b2 b1

ORER

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