R8CSLASH29 datasheet(272/471 Pages) RENESAS

272 / 471 page

R8C/28 Group, R8C/29 Group

16. Clock Synchronous Serial Interface

Rev.2.10

Sep 26, 2008

Page 255 of 441

REJ09B0279-0210

Figure 16.5

SSER Register

SS Enable Register

Symbol

Address

After Reset

SSER

00BBh

00h

Bit Symbol

Bit Name

Function

0 : Disables transmit end interrupt request

1 : Enables transmit end interrupt request

Receive enable bit

0 : Disables receive

1 : Enables receive

Transmit enable bit

0 : Disables transmit

1 : Enables transmit

0 : Disables receive data full and overrun

error interrupt request

1 : Enables receive data full and overrun

error interrupt request

Receive interrupt enable bit

TEIE

Transmit end interrupt enable bit

RIE

TIE

Transmit interrupt enable bit

0 : Disables transmit data empty interrupt

request

1 : Enables transmit data empty interrupt

request

Conflict error interrupt enable bit 0 : Disables conflict error interrupt request

1 : Enables conflict error interrupt request

—

(b2-b1)

Nothing is assigned. If necessary, set to 0.

When read, the content is 0.

CEIE

—

b7 b6 b5 b4

b3 b2 b1

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