R8CSLASH29 datasheet(267/471 Pages) RENESAS

267 / 471 page

R8C/28 Group, R8C/29 Group

16. Clock Synchronous Serial Interface

Rev.2.10

Sep 26, 2008

Page 250 of 441

REJ09B0279-0210

16.2

Clock Synchronous Serial I/O with Chip Select (SSU)

Clock synchronous serial I/O with chip select supports clock synchronous serial data communication.

Table 16.2 lists the Specifications of Clock Synchronous Serial I/O with Chip Select and Figure 16.1 shows a

Block Diagram of Clock Synchronous Serial I/O with Chip Select. Figures 16.2 to 16.9 show the registers

associated with clock synchronous serial I/O with chip select.

NOTE:

1. Clock synchronous serial I/O with chip select has only one interrupt vector table.

Table 16.2

Specifications of Clock Synchronous Serial I/O with Chip Select

Item

Specification

Transfer data format

• Transfer data length: 8 bits

Continuous transmission and reception of serial data are supported since both

transmitter and receiver have buffer structures.

Operating modes

• Clock synchronous communication mode

• 4-wire bus communication mode (including bidirectional communication)

Master/slave device

Selectable

I/O pins

SSCK (I/O): Clock I/O pin

SSI (I/O): Data I/O pin

SSO (I/O): Data I/O pin

SCS (I/O): Chip-select I/O pin

Transfer clocks

• When the MSS bit in the SSCRH register is set to 0 (operates as slave device),

external clock is selected (input from SSCK pin).

• When the MSS bit in the SSCRH register is set to 1 (operates as master

device), internal clock (selectable among f1/256, f1/128, f1/64, f1/32, f1/16, f1/8

and f1/4, output from SSCK pin) is selected.

• Clock polarity and phase of SSCK can be selected.

Receive error

detection

• Overrun error

Overrun error occurs during reception and completes in error. While the RDRF

bit in the SSSR register is set to 1 (data in the SSRDR register) and when next

serial data receive is completed, the ORER bit is set to 1.

Multimaster error

detection

• Conflict error

When the SSUMS bit in the SSMR2 register is set to 1 (4-wire bus

communication mode) and the MSS bit in the SSCRH register is set to 1

(operates as master device) and when starting a serial communication, the CE

bit in the SSSR register is set to 1 if “L” applies to the SCS pin input. When the

SSUMS bit in the SSMR2 register is set to 1 (4-wire bus communication

mode), the MSS bit in the SSCRH register is set to 0 (operates as slave

device) and the SCS pin input changes state from “L” to “H”, the CE bit in the

SSSR register is set to 1.

Interrupt requests

5 interrupt requests (transmit-end, transmit-data-empty, receive-data-full,

overrun error, and conflict error).(1)

Select functions

• Data transfer direction

Selects MSB-first or LSB-first

• SSCK clock polarity

Selects “L” or “H” level when clock stops

• SSCK clock phase

Selects edge of data change and data download

• SSI pin select function

The SSISEL bit in the PMR register can select P3_3 or P1_6 as SSI pin.

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