R8CSLASH29 datasheet(264/471 Pages) RENESAS

264 / 471 page

R8C/28 Group, R8C/29 Group

15. Serial Interface

Rev.2.10

Sep 26, 2008

Page 247 of 441

REJ09B0279-0210

15.2.1

Bit Rate

In UART mode, the bit rate is the frequency divided by the UiBRG (i = 0 or 1) register.

Figure 15.13

Calculation Formula of UiBRG (i = 0 or 1) Register Setting Value

i = 0 or 1

NOTE:

1. For the high-speed on-chip oscillator, the correction value in the FRA7 register should be written into the FRA1

This applies when the high-speed on-chip oscillator is selected as the system clock and bits FRA22 to FRA20 in

the FRA2 register are set to 000b (divide-by-2 mode). For the precision of the high-speed on-chip oscillator,

refer to 20. Electrical Characteristics.

Table 15.7

Bit Rate Setting Example in UART Mode (Internal Clock Selected)

Bit Rate

(bps)

UiBRG

Count

Source

System Clock = 20 MHz

System Clock = 18.432 MHz(1)

System Clock = 8 MHz

UiBRG

Setting

Value

Actual Time

(bps)

Setting

Error

(%)

UiBRG

Setting

Value

Actual Time

(bps)

Setting

Error

(%)

UiBRG

Setting

Value

Actual

Time

(bps)

Setting

Error

(%)

1200

129 (81h)

1201.92

0.16 119 (77h)

1200.00

0.00

51 (33h)

1201.92

0.16

2400

64 (40h)

2403.85

0.16

59 (3Bh)

2400.00

0.00

25 (19h)

2403.85

0.16

4800

32 (20h)

4734.85

-1.36

29 (1Dh)

4800.00

0.00

12 (0Ch)

4807.69

0.16

9600

129 (81h)

9615.38

0.16 119 (77h)

9600.00

0.00

51 (33h)

9615.38

0.16

14400

86 (56h)

14367.82

-0.22

79 (4Fh)

14400.00

0.00

34 (22h) 14285.71

-0.79

19200

64 (40h)

19230.77

0.16

59 (3Bh)

19200.00

0.00

25 (19h) 19230.77

0.16

28800

42 (2Ah)

29069.77

0.94

39 (27h)

28800.00

0.00

16 (10h) 29411.76

2.12

38400

32 (20h)

37878.79

-1.36

29 (1Dh)

38400.00

0.00

12 (0Ch) 38461.54

0.16

57600

21 (15h)

56818.18

-1.36

19 (13h)

57600.00

0.00

8 (08h) 55555.56

-3.55

115200

10 (0Ah)

113636.36

-1.36

9 (09h)

115200.00

0.00

−−

−

UART mode

• Internal clock selected

UiBRG register setting value =

Bit Rate

× 16

- 1

Fj: Count source frequency of the UiBRG register (f1, f8, or f32)

• External clock selected

fEXT

Bit Rate

× 16

- 1

fEXT: Count source frequency of the UiBRG register (external clock)

UiBRG register setting value =

i = 0 or 1

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