R8CSLASH29 datasheet(261/471 Pages) RENESAS

261 / 471 page

R8C/28 Group, R8C/29 Group

15. Serial Interface

Rev.2.10

Sep 26, 2008

Page 244 of 441

REJ09B0279-0210

i = 0 or 1

NOTES:

1. The bits used for transmit/receive data are as follows: Bits 0 to 6 when transfer data is 7 bits long;

bits 0 to 7 when transfer data is 8 bits long; bits 0 to 8 when transfer data is 9 bits long.

2. The following bits are undefined: Bits 7 and 8 when transfer data is 7 bits long; bit 8 when transfer

data is 8 bits long.

Table 15.6 lists the I/O Pin Functions in UART Mode. After the UARTi (i = 0 or 1) operating mode is selected, the

TXDi pin outputs “H” level. (If the NCH bit is set to 1 (N-channel open-drain output), this pin is in a high-

impedance state) until transfer starts.)

Table 15.5

Registers Used and Settings for UART Mode

Bit

Function

UiTB

0 to 8

Set transmit data(1)

UiRB

0 to 8

Receive data can be read(1, 2)

OER, FER, PER, SUM Error flag

UiBRG

0 to 7

Set a bit rate

UiMR

SMD2 to SMD0

Set to 100b when transfer data is 7 bits long.

Set to 101b when transfer data is 8 bits long.

Set to 110b when transfer data is 9 bits long.

CKDIR

Select the internal clock or external clock

STPS

Select the stop bit

PRY, PRYE

Select whether parity is included and whether odd or even

UiC0

CLK0 to CLK1

Select the count source for the UiBRG register

TXEPT

Transmit register empty flag

NCH

Select TXDi pin output mode

CKPOL

Set to 0

UFORM

LSB first or MSB first can be selected when transfer data is 8 bits

long. Set to 0 when transfer data is 7 or 9 bits long.

UiC1

Set to 1 to enable transmit

Transmit buffer empty flag

Set to 1 to enable receive

Receive complete flag

UiIRS

Select the source of UARTi transmit interrupt

UiRRM

Set to 0

Table 15.6

I/O Pin Functions in UART Mode

Pin name

Function

Selection Method

TXD0 (P1_4)

Output serial data

(Cannot be used as a port when performing reception only)

RXD0 (P1_5)

Input serial data

PD1_5 bit in PD1 register = 0

(P1_5 can be used as an input port when performing transmission only)

CLK0 (P1_6)

Programmable I/O Port CKDIR bit in U0MR register = 0

Input transfer clock

CKDIR bit in U0MR register = 1

PD1_6 bit in PD1 register = 0

TXD1 (P3_7)

Output serial data

Set registers PINSR1 and PMR (refer to Figure 15.7 Registers

PINSR1 and PMR

)

(Cannot be used as a port when performing reception only)

RXD1 (either

P3_7 or P4_5)

Input serial data

Set registers PINSR1 and PMR (refer to Figure 15.7 Registers

PINSR1 and PMR

)

Corresponding bit in each port direction register = 0

(Can be used as an input port when performing transmission only)

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