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R8C/29 Datasheet(PDF) 263 Page - Renesas Technology Corp |
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R8C/29 Datasheet(HTML) 263 Page - Renesas Technology Corp |
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263 / 471 page  R8C/28 Group, R8C/29 Group 15. Serial Interface Rev.2.10 Sep 26, 2008 Page 246 of 441 REJ09B0279-0210 Figure 15.12 Receive Timing Example in UART Mode UiBRG output Set to 0 when interrupt request is accepted, or set by a program • Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit) The above timing diagram applies when the register bits are set as follows: • PRYE bit in UiMR register = 0 (parity disabled) • STPS bit in UiMR register = 0 (1 stop bit) i = 0 or 1 UiC1 register RE bit Start bit Stop bit D0 D1 D7 RXDi Transfer clock Determined to be “L” Receive data taken in Reception triggered when transfer clock is generated by falling edge of start bit Transferred from UARTi receive register to UiRB register UiC1 register RI bit SiRIC register IR bit 1 0 1 0 1 0 |
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