R8CSLASH29 datasheet(245/471 Pages) RENESAS

245 / 471 page

R8C/28 Group, R8C/29 Group

14. Timers

Rev.2.10

Sep 26, 2008

Page 228 of 441

REJ09B0279-0210

14.4.3

Notes on Timer RE

14.4.3.1

Starting and Stopping Count

Timer RE has the TSTART bit for instructing the count to start or stop, and the TCSTF bit, which indicates

count start or stop. Bits TSTART and TCSTF are in the TRECR1 register.

Timer RE starts counting and the TCSTF bit is set to 1 (count starts) when the TSTART bit is set to 1 (count

starts). It takes up to 2 cycles of the count source until the TCSTF bit is set to 1 after setting the TSTART bit to

1. During this time, do not access registers associated with timer RE(1) other than the TCSTF bit.

Also, timer RE stops counting when setting the TSTART bit to 0 (count stops) and the TCSTF bit is set to 0

(count stops). It takes the time for up to 2 cycles of the count source until the TCSTF bit is set to 0 after setting

the TSTART bit to 0. During this time, do not access registers associated with timer RE other than the TCSTF

bit.

NOTE:

1. Registers associated with timer RE: TRESEC, TREMIN, TREHR, TREWK, TRECR1, TRECR2, and

TRECSR.

14.4.3.2

Write to the following registers or bits when timer RE is stopped.

• Registers TRESEC, TREMIN, TREHR, TREWK, and TRECR2

• Bits H12_H24, PM, and INT in TRECR1 register

• Bits RCS0 to RCS3 in TRECSR register

Timer RE is stopped when bits TSTART and TCSTF in the TRECR1 register are set to 0 (timer RE stopped).

Also, set all above-mentioned registers and bits (immediately before timer RE count starts) before setting the

TRECR2 register.

Figure 14.78 shows a Setting Example in Real-Time Clock Mode.

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