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R8C/29 Datasheet(PDF) 243 Page - Renesas Technology Corp |
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R8C/29 Datasheet(HTML) 243 Page - Renesas Technology Corp |
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243 / 471 page  R8C/28 Group, R8C/29 Group 14. Timers Rev.2.10 Sep 26, 2008 Page 226 of 441 REJ09B0279-0210 Figure 14.74 TRECR1 Register in Output Compare Mode Figure 14.75 TRECR2 Register in Output Compare Mode Timer RE Control Register 1 Symbol Address After Reset TRECR1 011Ch 00h Bit Symbol Bit Name Function RW b3 b2 INT b1 b0 00 — (b0) b7 b6 b5 b4 00 — TCSTF RO Nothing is assigned. If necessary, set to 0. When read, the content is 0. Timer RE count status flag 0 : Count stopped 1 : Counting RW TSTART Timer RE count start bit 0 : Count stops 1 : Count starts RW Interrupt request timing bit Set to 0 in output compare mode. PM A.m./p.m. bit TRERST Reserved bit Set to 0. — (b2) RW Timer RE reset bit When setting this bit to 0, after setting it to 1, the follow ing w ill occur. • Registers TRESEC, TREMIN, TREHR, TREWK, and TRECR2 are set to 00h. • Bits TCSTF, INT, PM, H12_H24, and TSTART in the TRECR1 register are set to 0. • The 8-bit counter is set to 00h and the 4-bit counter is set to 0h. RW RW H12_H24 Operating mode select bit RW Set to 0 in output compare mode. Timer RE Control Register 2 Symbol Address After Reset TRECR2 011Dh 00h Bit Symbol Bit Name Function RW — (b7-b6) — Nothing is assigned. If necessary, set to 0. When read, the content is 0. 0 : Disable compare match interrupt 1 : Enable compare match interrupt COMIE Compare match interrupt enable bit RW RW WKIE Periodic interrupt triggered every w eek enable bit Set to 0 in output compare mode. Periodic interrupt triggered every hour enable bit HRIE RW RW Periodic interrupt triggered every day enable bit RW MNIE RW Periodic interrupt triggered every minute enable bit Periodic interrupt triggered every second enable bit 0 b7 b6 b5 b4 b3 b2 DYIE b1 b0 00 00 SEIE |
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