R8CSLASH29 datasheet(241/471 Pages) RENESAS

241 / 471 page

R8C/28 Group, R8C/29 Group

14. Timers

Rev.2.10

Sep 26, 2008

Page 224 of 441

REJ09B0279-0210

14.4.2

Output Compare Mode

In output compare mode, the internal count source divided by 2 is counted using the 4-bit or 8-bit counter and

compare value match is detected with the 8-bit counter. Figure 14.71 shows a Block Diagram of Output

Compare Mode and Table 14.27 lists the Specifications of Output Compare Mode. Figures 14.72 to 14.76 show

the registers associated with output compare mode, and Figure 14.77 shows the Operating Example in Output

Compare Mode.

Figure 14.71

Block Diagram of Output Compare Mode

NOTE:

1. For J, K version, fC4 cannot be selected.

Table 14.27

Specifications of Output Compare Mode

Item

Specification

Count sources

f4, f8, f32, fC4(1)

Count operations

• Increment

• When the 8-bit counter content matches with the TREMIN register content,

the value returns to 00h and count continues. The count value is held while

count stops.

Count period

• When RCS2 = 0 (4-bit counter is not used)

1/fi x 2 x (n+1)

• When RCS2 = 1 (4-bit counter is used)

1/fi x 32 x (n+1)

fi: Frequency of count source

n: Setting value of TREMIN register

Count start condition

1 (count starts) is written to the TSTART bit in the TRECR1 register

Count stop condition

0 (count stops) is written to the TSTART bit in the TRECR1 register

Interrupt request

generation timing

When the 8-bit counter content matches with the TREMIN register content

Read from timer

When reading the TRESEC register, the 8-bit counter value can be read.

When reading the TREMIN register, the compare value can be read.

Write to timer

Writing to the TRESEC register is disabled.

When bits TSTART and TCSTF in the TRECR1 register are set to 0 (timer

stops), writing to the TREMIN register is enabled.

Select functions

Select use of 4-bit counter

fC4(1)

f32

4-bit

counter

8-bit

counter

TRESEC

TREMIN

1/2

RCS2 = 1

RCS2 = 0

COMIE

Timer RE interrupt

Match

signal

= 00b

= 01b

= 10b

= 11b

RCS1 to RCS0

TRERST, TOENA: Bits in TRECR1 register

COMIE: Bit in TRECR2 register

RCS0 to RCS2: Bits in TRECSR register

Reset

TRERST bit

Data bus

Comparison

circuit

NOTE:

1. For J, K version, fC4 cannot be selected.

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