R8CSLASH29 datasheet(237/471 Pages) RENESAS

237 / 471 page

R8C/28 Group, R8C/29 Group

14. Timers

Rev.2.10

Sep 26, 2008

Page 220 of 441

REJ09B0279-0210

Figure 14.66

TRECR1 Register in Real-Time Clock Mode

Figure 14.67

Definition of Time Representation

Timer RE Control Register 1

Symbol

Address

After Reset

TRECR1

011Ch

00h

Bit Symbol

Bit Name

Function

NOTE:

b3 b2

INT

b1 b0

—

(b0)

b7 b6 b5 b4

—

TCSTF

Nothing is assigned. If necessary, set to 0.

When read, the content is 0.

Timer RE count status flag

0 : Count stopped

1 : Counting

Reserved bit

Set to 0.

This bit is automatically modified w hile timer RE counts.

—

(b2)

TSTART

Timer RE count start bit

0 : Count stops

1 : Count starts

Interrupt request timing bit

Set to 1 in real-time clock mode.

A.m./p.m. bit

When the H12_H24 bit is set to 0

(12-hour mode)(1)

0 : a.m.

1 : p.m.

When the H12_H24 bit is set to 1 (24-hour

mode), its value is undefined.

TRERST

Timer RE reset bit

When setting this bit to 0, after setting it to 1, the

follow ings w ill occur.

• Registers TRESEC, TREMIN, TREHR, TREWK,

and TRECR2 are set to 00h.

• Bits TCSTF, INT, PM, H12_H24, and TSTART

in the TRECR1 register are set to 0.

• The 8-bit counter is set to 00h and

the 4-bit counter is set to 0h.

H12_H24

Operating mode select bit

0 : 12-hour mode

1 : 24-hour mode

Noon

H12_H24 bit = 1

(24-hour mode)

Contents of PM bit

0 (a.m.)

1 (p.m.)

Contents of

TREHR Register

H12_H24 bit = 0

(12-hour mode)

Contents in TREWK register

000 (Sunday)

H12_H24 bit = 1

(24-hour mode)

Contents of PM bit

1 (p.m.)

Contents of

TREHR Register

H12_H24 bit = 0

(12-hour mode)

Contents in TREWK register

000 (Sunday)

⋅⋅⋅

Date changes

⋅⋅⋅

0 (a.m.)

001 (Monday)

⋅⋅⋅

PM bit and H12_H24 bits: Bits in TRECR1 register

The above applies to the case when count starts from a.m. 0 on Sunday.

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