R8CSLASH29 datasheet(244/471 Pages) RENESAS

244 / 471 page

R8C/28 Group, R8C/29 Group

14. Timers

Rev.2.10

Sep 26, 2008

Page 227 of 441

REJ09B0279-0210

Figure 14.76

TRECSR Register in Output Compare Mode

Figure 14.77

Operating Example in Output Compare Mode

Timer RE Count Source Select Register

Symbol

Address

After Reset

TRECSR

011Eh

00001000b

Bit Symbol

Bit Name

Function

NOTE:

1. For J, K version, fC4 cannot be selected.

—

(b7)

—

Real-time clock mode select bit

Set to 0 in output compare mode.

Nothing is assigned. If necessary, set to 0.

When read, the content is 0.

—

(b4)

Nothing is assigned. If necessary, set to 0.

When read, the content is 0.

4-bit counter select bit

0 : Not used

1 : Used

RCS2

RCS1

Count source select bits

b1 b0

0 0 : f4

0 1 : f8

1 0 : f32

1 1 : fC4(1)

b7 b6 b5 b4 b3 b2

RCS3

b1 b0

RCS0

—

(b6-b5)

Reserved bits

Set to 00b.

00h

Count starts

Time

TSTART bit in

TRECR1 register

IR bit in

TREIC register

The above applies under the following conditions.

TOENA bit in TRECR1 register = 1 (enable clock output)

COMIE bit in TRECR2 register = 1 (enable compare match interrupt)

RCS6 to RCS5 bits in TRECSR register = 11b (compare output)

Set to

1 by a program

TREMIN register

setting value

Matched

TCSTF bit in

TRECR1 register

Matched

Set to

0 by acknowledgement of interrupt request or a program

2 cycles of maximum count source

R8C/29 Datasheet(PDF) 244 Page - Renesas Technology Corp

R8C/29 Datasheet(HTML) 244 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL