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R8C/29 Datasheet(PDF) 278 Page - Renesas Technology Corp |
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R8C/29 Datasheet(HTML) 278 Page - Renesas Technology Corp |
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278 / 471 page  R8C/28 Group, R8C/29 Group 16. Clock Synchronous Serial Interface Rev.2.10 Sep 26, 2008 Page 261 of 441 REJ09B0279-0210 Figure 16.10 Association between Transfer Clock Polarity, Phase, and Transfer Data SSCK b0 SSO, SSI • SSUMS = 0 (clock synchronous communication mode), CPHS bit = 0 (data change at odd edge), and CPOS bit = 0 (“H” when clock stops) b1 b2 b3 b4 b5 b6 b7 SSCK CPOS = 0 (“H” when clock stops) b0 SSO, SSI • SSUMS = 1 (4-wire bus communication mode) and CPHS = 0 (data change at odd edge) b1 b2 b3 b4 b5 b6 b7 SSCK CPOS = 1 (“L” when clock stops) SCS SSCK CPOS = 0 (“H” when clock stops) SSO, SSI • SSUMS = 1 (4-wire bus communication mode) and CPHS = 1 (data download at odd edge) SSCK CPOS = 1 (“L” when clock stops) SCS b0 b1 b2 b3 b4 b5 b6 b7 CPHS and CPOS: Bits in SSMR register, SSUMS: Bits in SSMR2 register |
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