R8CSLASH29 datasheet(252/471 Pages) RENESAS

252 / 471 page

R8C/28 Group, R8C/29 Group

15. Serial Interface

Rev.2.10

Sep 26, 2008

Page 235 of 441

REJ09B0279-0210

Figure 15.5

Registers U0C0 to U1C0

UARTi Transmit/Receive Control Register 0 (i = 0 or 1)

Symbol

Address

After Reset

U0C0

00A4h

00001000b

U1C0

00ACh

00001000b

Bit Symbol

Bit Name

Function

NOTE:

b3 b2

TXEPT

b1 b0

CLK0

—

Reserved bit

b7 b6 b5 b4

—

(b2)

CKPOL

CLK1

BRG count source select

bits(1)

b1 b0

0 0 : Selects f1

0 1 : Selects f8

1 0 : Selects f32

1 1 : Do not set.

—

(b4)

CLK polarity select bit

0 : Transmit data is output at falling edge of transfer

clock and receive data is input at rising edge

1 : Transmit data is output at rising edge of transfer

clock and receive data is input at falling edge

Set to 0.

Transmit register empty

flag

0 : Data in transmit register (during transmit)

1 : No data in transmit register (transmit completed)

Nothing is assigned. If necessary, set to 0.

When read, the content is 0.

If the BRG count source is sw itched, set the UiBRG register again.

Data output select bit

0 : TXDi pin is for CMOS output

1 : TXDi pin is for N-channel open drain output

UFORM

Transfer format select bit 0 : LSB first

1 : MSB first

NCH

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