R8CSLASH29 datasheet(256/471 Pages) RENESAS

256 / 471 page

R8C/28 Group, R8C/29 Group

15. Serial Interface

Rev.2.10

Sep 26, 2008

Page 239 of 441

REJ09B0279-0210

NOTE:

1. Set bits which are not in this table to 0 when writing to the above registers in clock synchronous

serial I/O mode.

Table 15.3 lists the I/O Pin Functions in Clock Synchronous Serial I/O Mode. The TXD0 pin outputs “H” level

between the operating mode selection of UART0 and transfer start. (If the NCH bit is set to 1 (N-channel open-

drain output), this pin is in a high-impedance state.)

Table 15.2

Registers Used and Settings in Clock Synchronous Serial I/O Mode(1)

Bit

Function

U0TB

0 to 7

Set data transmission

U0RB

0 to 7

Data reception can be read

OER

Overrun error flag

U0BRG

0 to 7

Set bit rate

U0MR

SMD2 to SMD0

Set to 001b

CKDIR

Select the internal clock or external clock

U0C0

CLK1 to CLK0

Select the count source in the UiBRG register

TXEPT

Transmit register empty flag

NCH

Select TXD0 pin output mode

CKPOL

Select the transfer clock polarity

UFORM

Select the LSB first or MSB first

U0C1

Set this bit to 1 to enable transmission/reception

Transmit buffer empty flag

Set this bit to 1 to enable reception

Reception complete flag

U0IRS

Select the UART0 transmit interrupt source

U0RRM

Set this bit to 1 to use continuous receive mode

Table 15.3

I/O Pin Functions in Clock Synchronous Serial I/O Mode

Pin Name

Function

Selection Method

TXD0 (P1_4)

Output serial data

(Outputs dummy data when performing reception only)

RXD0 (P1_5)

Input serial data

PD1_5 bit in PD1 register = 0

(P1_5 can be used as an input port when performing

transmission only)

CLK0 (P1_6)

Output transfer clock

CKDIR bit in U0MR register = 0

Input transfer clock

CKDIR bit in U0MR register = 1

PD1_6 bit in PD1 register = 0

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