HD6417618A datasheet(185/646 Pages) RENESAS

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Section 7 Bus State Controller (BSC)

Rev. 6.00 Jun. 12, 2007 Page 153 of 610

REJ09B0131-0600

7.5.5

SDRAM Interface

SDRAM Direct Connection: The SDRAM that can be connected to this LSI is a product that has

11/12/13 bits of row address, 8/9/10 bits of column address, 4 or less banks, and uses the A10 pin

for setting precharge mode in read and write command cycles.

The control signals for direct connection of SDRAM are

RAS, CAS, RD/WR, DQMLU, DQMLL,

CKE, and

CS3. Signals other than CKE are valid when CS3 is asserted. SDRAM can be connected

to area 2. The data bus width of the area that is connected to SDRAM can be set to 16 bits.

Burst read/single write (burst length 1) and burst read/burst write (burst length 1) are supported as

the SDRAM operating mode.

Commands for SDRAM can be specified by

RAS, CAS, RD/WR, and specific address signals.

These commands are shown below.

• NOP

• Auto-refreshing (REF)

• Self-refreshing (SELF)

• All banks precharge (PALL)

• Specified bank precharge (PRE)

• Bank active (ACTV)

• Read (READ)

• Read with precharge (READA)

• Write (WRIT)

• Write with precharge (WRITA)

• Write mode register (MRS)

The byte to be accessed is specified by DQMLU and DQMLL. Reading or writing is performed

for a byte whose corresponding DQMxx is low. For details on the relationship between DQMxx

and the byte to be accessed, refer to section 7.5.1, Endian/Access Size and Data Alignment.

HD6417618A Datasheet(PDF) 185 Page - Renesas Technology Corp