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HD6417618A Datasheet(PDF) 61 Page - Renesas Technology Corp

Part # HD6417618A
Description  32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
PDF  646 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD6417618A Datasheet(HTML) 61 Page - Renesas Technology Corp

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Section 2 CPU
Rev. 6.00 Jun. 12, 2007 Page 29 of 610
REJ09B0131-0600
Addressing
Mode
Instruction
Format
Effective Address Calculation Method
Calculation
Formula
Register
indirect with
pre-decrement
@–Rn
Effective address is register Rn contents,
decremented by a constant beforehand: 1 for a
byte operand, 2 for a word operand, 4 for a
longword operand.
Rn
Rn - 1/2/4
1/2/4
-
Rn - 1/2/4
Byte: Rn – 1
→
Rn
Word: Rn – 2
→
Rn
Longword: Rn – 4
→ Rn
(Instruction
executed with Rn
after calculation)
Register
indirect with
displacement
@(disp:4,
Rn)
Effective address is register Rn contents with
4-bit displacement disp added. After disp is
zero-extended, it is multiplied by 1 (byte), 2
(word), or 4 (longword), according to the
operand size.
1/2/4
×
disp
(zero-extended)
Rn
+ disp
× 1/2/4
+
Rn
Byte: Rn + disp
Word: Rn + disp
×
2
Longword: Rn +
disp
× 4
Index
register indirect
@(R0, Rn) Effective address is sum of register Rn and R0
contents.
+
Rn
R0
Rn
+ R0
Rn + R0
GBR indirect
with
displacement
@(disp:8,
GBR)
Effective address is register GBR contents with
8-bit displacement disp added. After disp is
zero-extended, it is multiplied by 1 (byte), 2
(word), or 4 (longword), according to the
operand size.
GBR
1/2/4
disp
(zero-extended)
GBR
+ disp
× 1/2/4
×
+
Byte: GBR + disp
Word: GBR + disp
× 2
Longword: GBR +
disp
× 4



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