HD6417618A datasheet(54/646 Pages) RENESAS

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Section 2 CPU

Rev. 6.00 Jun. 12, 2007 Page 22 of 610

REJ09B0131-0600

Bit

name

Default

Read/

Write

Description

Undefined

R/W

Indicates true (1) or false (0) in the following

instructions: MOVT, CMP/cond, TAS, TST, BT (BT/S),

BF (BF/S), SETT, CLRT

Indicates carry, borrow, overflow, or underflow in the

following instructions: ADDV, ADDC, SUBV, SUBC,

NEGC, DIV0U, DIV0S, DIV1, SHAR, SHAL, SHLR,

SHLL, ROTR, ROTL, ROTCR, ROTCL

• Global-base register (GBR)

This register indicates a base address in GBR indirect addressing mode. The GBR indirect

addressing mode is used for data transfer of the on-chip peripheral module registers and logic

operations.

• Vector-base register (VBR)

This register indicates the base address of the exception handling vector table.

2.2.3

System Registers

There are four 32-bit system registers, designated two multiply and accumulate registers (MACH

and MACL), a procedure register (PR), and program counter (PC).

• Multiply and accumulate registers (MAC)

This register stores the results of multiplication and multiply-and-accumulate operation.

• Procedure register (PR)

This register stores the return-destination address from subroutine procedures.

• Program counter (PC)

The PC indicates the point which is four bytes (two instructions) after the current execution

instruction.

HD6417618A Datasheet(PDF) 54 Page - Renesas Technology Corp