HD6417618A datasheet(100/646 Pages) RENESAS

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Section 5 Exception Handling

Rev. 6.00 Jun. 12, 2007 Page 68 of 610

REJ09B0131-0600

Exception Handling Source

Vector Number

Vector Table Address Offset

Trap instruction (user vector)

H'00000080 to H'00000083

H'000000FC to H'000000FF

Interrupt

IRQ0

H'00000100 to H'00000103

IRQ1

H'00000104 to H'00000107

IRQ2

H'00000108 to H'0000010B

IRQ3

H'0000010C to H'0000010F

(Reserved by system)

H'00000110 to H'00000113

H'0000013C to H'0000013F

IRQ4

H'00000140 to H'00000143

IRQ5

H'00000144 to H'00000147

IRQ6

H'00000148 to H'0000014B

IRQ7

H'0000014C to H'0000014F

On-chip peripheral module*

H'00000120 to H'00000124

255

H'000003FC to H'000003FF

Note:

For details on the vector numbers and vector table address offsets of on-chip peripheral

module interrupts, see table 6.2, Interrupt Exception Handling Vectors and Priorities in

section 6, Interrupt Controller (INTC).

Table 5.4

Calculating Exception Handling Vector Table Addresses

Exception Source

Vector Table Address Calculation

Resets

Vector table address = H'A0000000

+ (vector table address offset)

= H'A0000000

+ (vector number) × 4

Address errors, interrupts,

instructions

Vector table address = VBR + (vector table address offset)

= VBR + (vector number)

× 4

Notes: 1. VBR: Vector base register

2. Vector table address offset: See table 5.3.

3. Vector number: See table 5.3.

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