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HD6417618A Datasheet(PDF) 77 Page - Renesas Technology Corp

Part # HD6417618A
Description  32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
PDF  646 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD6417618A Datasheet(HTML) 77 Page - Renesas Technology Corp

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Section 2 CPU
Rev. 6.00 Jun. 12, 2007 Page 45 of 610
REJ09B0131-0600
Instruction
Operation
Code
Execution
Cycles
T Bit
BRAF
Rm
Delayed branch,
Rm + PC
→ PC
0000mmmm00100011
2
BSR
label
Delayed branch, PC
→ PR,
disp
× 2 + PC → PC
1011dddddddddddd
2
BSRF
Rm
Delayed branch, PC
→ PR,
Rm + PC
→ PC
0000mmmm00000011
2
JMP
@Rm
Delayed branch, Rm
→ PC 0100mmmm00101011 2
JSR
@Rm
Delayed branch, PC
→ PR,
Rm
→ PC
0100mmmm00001011
2
RTS
Delayed branch, PR
→ PC
0000000000001011
2
Note:
*
One cycle when the branch is not executed.
• System Control Instructions
Instruction
Operation
Code
Execution
Cycles
T Bit
CLRT
0
→ T
0000000000001000
1
0
CLRMAC
0
→ MACH, MACL
0000000000101000
1
LDC
Rm,SR
Rm
→ SR
0100mmmm00001110
6
LSB
LDC
Rm,GBR
Rm
→ GBR
0100mmmm00011110
4
LDC
Rm,VBR
Rm
→ VBR
0100mmmm00101110
4
LDC.L @Rm+,SR
(Rm)
→ SR, Rm + 4 → Rm 0100mmmm00000111
8
LSB
LDC.L @Rm+,GBR
(Rm)
→ GBR, Rm + 4 →
Rm
0100mmmm00010111
4
LDC.L @Rm+,VBR
(Rm)
→ VBR, Rm + 4 →
Rm
0100mmmm00100111
4
LDS
Rm,MACH
Rm
→ MACH
0100mmmm00001010
1
LDS
Rm,MACL
Rm
→ MACL
0100mmmm00011010
1
LDS
Rm,PR
Rm
→ PR
0100mmmm00101010
1
LDS.L @Rm+,MACH
(Rm)
→ MACH, Rm + 4 →
Rm
0100mmmm00000110
1
LDS.L @Rm+,MACL
(Rm)
→ MACL, Rm + 4 →
Rm
0100mmmm00010110
1
LDS.L @Rm+,PR
(Rm)
→ PR, Rm + 4 → Rm 0100mmmm00100110
1



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