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HD6417618A Datasheet(PDF) 85 Page - Renesas Technology Corp |
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HD6417618A Datasheet(HTML) 85 Page - Renesas Technology Corp |
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85 / 646 page  Section 3 Cache Rev. 6.00 Jun. 12, 2007 Page 53 of 610 REJ09B0131-0600 Bit Bit Name Initial Value R/W Description 0 CE 0 R/W Cache Enable Indicates whether or not the cache function is used. 0: Cache function is not used. 1: Cache function is used. 3.2.2 Cache Control Register 3 (CCR3) CCR3 specifies the cache size. Programs that change the contents of CCR3 should be placed in the address space that is not cached. Note: Supported only by the SH7618. Bit Bit Name Initial Value R/W Description 31 to 17 — All 0 R Reserved These bits are always read as 0. The write value should always be 0. 16 15 14 CSIZE2 CSIZE1 CSIZE0 0 0 1 R/W R/W R/W Cache Size Writing B'100 to these bits specifies the cache size 16 kbytes. Write B'100 before enabling the cache by the CE bit in CCR1. 13 to 0 — All 0 R Reserved These bits are always read as 0. The write value should always be 0. |
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