Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.COM

X  

Preview PDF HTML

HD6417618A Datasheet(PDF) 78 Page - Renesas Technology Corp

Part # HD6417618A
Description  32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
PDF  646 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD6417618A Datasheet(HTML) 78 Page - Renesas Technology Corp

Back Button HD6417618A Datasheet HTML 74Page - Renesas Technology Corp HD6417618A Datasheet HTML 75Page - Renesas Technology Corp HD6417618A Datasheet HTML 76Page - Renesas Technology Corp HD6417618A Datasheet HTML 77Page - Renesas Technology Corp HD6417618A Datasheet HTML 78Page - Renesas Technology Corp HD6417618A Datasheet HTML 79Page - Renesas Technology Corp HD6417618A Datasheet HTML 80Page - Renesas Technology Corp HD6417618A Datasheet HTML 81Page - Renesas Technology Corp HD6417618A Datasheet HTML 82Page - Renesas Technology Corp Next Button
Zoom Inzoom in Zoom Outzoom out
 78 / 646 page
background image
Section 2 CPU
Rev. 6.00 Jun. 12, 2007 Page 46 of 610
REJ09B0131-0600
Instruction
Operation
Code
Execution
Cycles
T Bit
NOP
No operation
0000000000001001
1
RTE
Delayed branch,
Stack area
→ PC/SR
0000000000101011
5
SETT
1
→ T
0000000000011000
1
1
SLEEP
Sleep
0000000000011011
4*
STC
SR,Rn
SR
→ Rn
0000nnnn00000010
1
STC
GBR,Rn
GBR
→ Rn
0000nnnn00010010
1
STC
VBR,Rn
VBR
→ Rn
0000nnnn00100010
1
STC.L SR,@
–Rn
Rn–4
→ Rn, SR → (Rn)
0100nnnn00000011
1
STC.L GBR,@
–Rn
Rn–4
→ Rn, GBR → (Rn)
0100nnnn00010011
1
STC.L VBR,@
–Rn
Rn–4
→ Rn, VBR → (Rn)
0100nnnn00100011
1
STS
MACH,Rn
MACH
→ Rn
0000nnnn00001010
1
STS
MACL,Rn
MACL
→ Rn
0000nnnn00011010
1
STS
PR,Rn
PR
→ Rn
0000nnnn00101010
1
STS.L MACH,@
–Rn
Rn–4
→ Rn, MACH → (Rn) 0100nnnn00000010
1
STS.L MACL,@
–Rn
Rn–4
→ Rn, MACL → (Rn) 0100nnnn00010010
1
STS.L PR,@
–Rn
Rn–4
→ Rn, PR → (Rn)
0100nnnn00100010
1
TRAPA #imm
PC
/SR → Stack area,
(imm
× 4 + VBR) → PC
11000011iiiiiiii
8
Note:
*
Number of execution cycles until this LSI enters sleep mode.
About the number of execution cycles:
The table lists the minimum number of execution cycles. In practice, the number of
execution cycles will be increased depending on the conditions such as:
• When there is a conflict between instruction fetch and data access
• When the destination register of a load instruction (memory → register) is also used
by the instruction immediately after the load instruction.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link to Datasheet   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com