HD6417618A datasheet(36/646 Pages) RENESAS

36 / 646 page

Section 1 Overview

Rev. 6.00 Jun. 12, 2007 Page 4 of 610

REJ09B0131-0600

 Peripheral clock: 50 MHz (max.)

• Supports power-down modes:

 Sleep mode

 Software standby mode

• Selection of four types of clock modes (PLL2 ×2/×4 and clock/crystal resonator are selectable)

Ethernet controller (EtherC):

• MAC (Media Access Control) function

 Data frame assembly/disassembly (frame format conforming to IEEE802.3u)

 CSMA/CD link management (collision prevention and collision processing)

 CRC processing

 On-chip FIFOs (256 bytes (SH7618) and 512 bytes (SH7618A), each for transmit/receive

operation)

 Full-duplex transmit/receive support

 Short frame/long frame detectable

• Conforms to the MII (Media Independent Interface) standard

 Conversion from 8-bit stream data in MAC layer to MII nibble (4-bit) stream

 Station management (STA function)

 18 TTL-level signals

 10/100 Mbps transfer rate adjustable

• Magic PacketTM* (WOL (Wake-On-LAN) output)

Ethernet controller DMAC (EDMAC):

• CPU load reduced with the descriptor management method

• For transferring from EtherC receive FIFO to receive buffer × 1 channel

• For transferring from transmit buffer to EtherC transmit FIFO × 1 channel

• 16-byte burst transfer improves the efficiency of system bus

• Supports single frame and multiple buffer

Host interface (HIF):

• 1 kbyte × 2 banks: in total 2-kbyte buffer RAM

• The buffer RAM and the external device are connected in parallel via 16 data pins

• The buffer RAM and the CPU of this LSI are connected in parallel via internal bus

HD6417618A Datasheet(PDF) 36 Page - Renesas Technology Corp