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HD6417618A Datasheet(PDF) 21 Page - Renesas Technology Corp |
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HD6417618A Datasheet(HTML) 21 Page - Renesas Technology Corp |
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21 / 646 page  Rev. 6.00 Jun. 12, 2007 Page xxi of xxxii Figures Section 1 Overview Figure 1.1 Block Diagram .............................................................................................................. 6 Figure 1.2 Pin Assignments............................................................................................................ 7 Section 2 CPU Figure 2.1 CPU Internal Register Configuration .......................................................................... 20 Figure 2.2 Register Data Format................................................................................................... 24 Figure 2.3 Memory Data Format .................................................................................................. 24 Figure 2.4 CPU State Transition................................................................................................... 47 Section 3 Cache Figure 3.1 Cache Structure ........................................................................................................... 49 Figure 3.2 Cache Search Scheme ................................................................................................. 55 Figure 3.3 Write-Back Buffer Configuration................................................................................ 57 Figure 3.4 Specifying Address and Data for Memory-Mapped Cache Access............................. 60 Section 6 Interrupt Controller (INTC) Figure 6.1 INTC Block Diagram .................................................................................................. 82 Figure 6.2 Block Diagram of IRQ7 to IRQ0 Interrupts Control................................................... 96 Figure 6.3 Interrupt Sequence Flowchart.................................................................................... 101 Figure 6.4 Stack after Interrupt Exception Handling.................................................................. 102 Section 7 Bus State Controller (BSC) Figure 7.1 Block Diagram of BSC.............................................................................................. 107 Figure 7.2 Address Space ........................................................................................................... 110 Figure 7.3 Normal Space Basic Access Timing (No-Wait Access)............................................ 146 Figure 7.4 Consecutive Access to Normal Space (1): Bus Width = 16 bits, Longword Access, CSnWCR.WM = 0 (Access Wait = 0, Cycle Wait = 0) ............. 147 Figure 7.5 Consecutive Access to Normal Space (2): Bus Width = 16 bits, Longword Access, CSnWCR.WM = 1 (Access Wait = 0, Cycle Wait = 0) ............. 148 Figure 7.6 Example of 16-Bit Data-Width SRAM Connection.................................................. 149 Figure 7.7 Example of 8-Bit Data-Width SRAM Connection.................................................... 149 Figure 7.8 Wait Timing for Normal Space Access (Software Wait Only) ................................. 150 Figure 7.9 Wait Cycle Timing for Normal Space Access (Wait cycle Insertion using WAIT)..151 Figure 7.10 Example of Timing when CSn Assertion Period is Extended .................................152 Figure 7.11 Example of 16-Bit Data-Width SDRAM Connection ............................................. 154 Figure 7.12 Burst Read Basic Timing (Auto Precharge) ............................................................ 162 Figure 7.13 Burst Read Wait Specification Timing (Auto Precharge) ....................................... 163 Figure 7.14 Basic Timing for Single Read (Auto Precharge)..................................................... 164 |
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