HD6417618A datasheet(58/646 Pages) RENESAS

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Section 2 CPU

Rev. 6.00 Jun. 12, 2007 Page 26 of 610

REJ09B0131-0600

Load/Store Architecture: Basic operations are executed between registers. In operations

involving memory, data is first loaded into a register (load/store architecture). However, bit

manipulation instructions such as AND are executed directly in memory.

Delayed Branching: Unconditional branch instructions means the delayed branch instructions.

With a delayed branch instruction, the branch is made after execution of the instruction

immediately following the delayed branch instruction. This minimizes disruption of the pipeline

when a branch is made. The conditional branch instructions have two types of instructions:

conditional branch instructions and delayed branch instructions.

Table 2.3

Delayed Branch Instructions

CPU in this LSI

Description

Example of Other CPUs

BRA

TRGET

ADD

R1,R0

ADD is executed before branch to TRGET.

ADD.W R1,R0

BRA

TRGET

Multiply/Multiply-and-Accumulate Operations: A 16

× 16 → 32 multiply operation is

executed in one to two cycles, and a 16

× 16 + 64 → 64 multiply-and-accumulate operation in two

to three cycles. A 32

× 32 → 64 multiply operation and a 32 × 32 + 64 → 64 multiply-and-

accumulate operation are each executed in two to four cycles.

T Bit: The result of a comparison is indicated by the T bit in SR, and a conditional branch is

performed according to whether the result is True or False. Processing speed has been improved

by keeping the number of instructions that modify the T bit to a minimum.

Table 2.4

T Bit

CPU in this LSI

Description

Example of Other CPUs

CMP/GE

R1,R0

When R0

≥ R1, the T bit is set.

CMP.W R1,R0

TRGET0

When R0

≥ R1, a branch is made to TRGET0. BGE

TRGET0

TRGET1

When R0 < R1, a branch is made to TRGET1. BLT

TRGET1

ADD

−1,R0

The T bit is not changed by ADD.

SUB.W #1,R0

CMP/EQ

#0,R0

When R0 = 0, the T bit is set.

BEQ

TRGET

A branch is made when R0 = 0.

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