+2.7V, Low-Power, Multichannel,

Serial 8-Bit ADCs

14

______________________________________________________________________________________

SSTRB

CS

SCLK

DIN

DOUT

14

8

12

15

17

START

SEL2 SEL1 SEL0

UNI/

BIP

SGL/

DIF

PD1

PD0

B7

B6

B1

B0

IDLE

FILLED WITH

ZEROS

IDLE

CONVERSION

25µs TYP

A/D STATE

2

3

5

6

7

9

10

11

16

18

Figure 10. Internal Clock Mode Timing

PD0 CLOCK IN

SSTRB

SCLK

NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION.

CS

Figure 11. Internal Clock Mode SSTRB Detailed Timing

Internal Clock

Internal clock mode frees the µP from the burden of

running the SAR conversion clock. This allows the con-

version results to be read back at the processor’s con-

venience, at any clock rate up to 2MHz. SSTRB goes

low at the start of the conversion and then goes high

when the conversion is complete. SSTRB is low for

25µs (typically), during which time SCLK should remain

low for best noise performance.

An internal register stores data when the conversion is

in progress. SCLK clocks the data out of this register at

any time after the conversion is complete. After SSTRB

goes high, the second falling clock edge produces the

MSB of the conversion at DOUT, followed by the

remaining bits in MSB-first format (Figure 10). CS does

not need to be held low once a conversion is started.

Pulling CS high prevents data from being clocked into

the MAX1110/MAX1111 and three-states DOUT, but it

does not adversely affect an internal clock-mode con-

version already in progress. When internal clock mode

is selected, SSTRB does not go into a high-impedance

state when CS goes high.

Figure 11 shows the SSTRB timing in internal clock

mode. In this mode, data can be shifted in and out of

the MAX1110/MAX1111 at clock rates up to 2MHz, pro-

above 1µs.