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HD6417618A Datasheet(PDF) 169 Page - Renesas Technology Corp |
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HD6417618A Datasheet(HTML) 169 Page - Renesas Technology Corp |
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169 / 646 page  Section 7 Bus State Controller (BSC) Rev. 6.00 Jun. 12, 2007 Page 137 of 610 REJ09B0131-0600 Bit Bit Name Initial Value R/W Description 4 3 A3ROW1 A3ROW0 0 0 R/W R/W Number of Bits of Row Address for Area 3 Specify the number of bits of the row address for area 3. 00: 11 bits 01: 12 bits 10: 13 bits 11: Reserved (setting prohibited) 2 0 R Reserved This bit is always read as 0. The write value should always be 0. 1 0 A3COL1 A3COL0 0 0 R/W R/W Number of Bits of Column Address for Area 3 Specify the number of bits of the column address for area 3. 00: 8 bits 01: 9 bits 10: 10 bits 11: Reserved (setting prohibited) 7.4.5 Refresh Timer Control/Status Register (RTCSR) RTCSR specifies various items about refresh for SDRAM. When RTCSR is written to, the upper 16 bits of the write data must be H'A55A to cancel write protection. Bit Bit Name Initial Value R/W Description 31 to 8 All 0 R Reserved These bits are always read as 0. The write value should always be 0. |
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