HD6417618A datasheet(168/646 Pages) RENESAS

168 / 646 page

Section 7 Bus State Controller (BSC)

Rev. 6.00 Jun. 12, 2007 Page 136 of 610

REJ09B0131-0600

7.4.4

SDRAM Control Register (SDCR)

SDCR specifies the method to refresh and access SDRAM, and the types of SDRAMs to be

connected.

Bit

Bit Name

Initial

Value

R/W

Description

31 to 12



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

RFSH

R/W

Refresh Control

Specifies whether or not the refreshing SDRAM is

performed.

0: Refreshing is not performed

1: Refreshing is performed

RMODE

R/W

Refresh Control

Specifies whether to perform auto-refreshing or

self-refreshing when the RFSH bit is 1. When the RFSH

bit is 1 and this bit is 1, self-refreshing starts immediately.

When the RFSH bit is 1 and this bit is 0, auto-refreshing

starts according to the contents that are set in RTCSR,

RTCNT, and RTCOR.

0: Auto-refreshing is performed

1: Self-refreshing is performed



Reserved

This bit is always read as 0. The write value should

always be 0.

BACTV

R/W

Bank Active Mode

Specifies whether to access in auto-precharge mode

(using READA and WRITA commands) or in bank active

mode (using READ and WRIT commands).

0: Auto-precharge mode (using READA and WRITA

commands)

1: Bank active mode (using READ and WRIT commands)

7 to 5



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

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