HD6417618A datasheet(105/646 Pages) RENESAS

105 / 646 page

Section 5 Exception Handling

Rev. 6.00 Jun. 12, 2007 Page 73 of 610

REJ09B0131-0600

5.4.2

Interrupt Priority

The interrupt priority is predetermined. When multiple interrupts occur simultaneously

(overlapped interruptions), the interrupt controller (INTC) determines their relative priorities and

starts the exception handling according to the results.

The priority of interrupts is expressed as priority levels 0 to 16, with priority 0 the lowest and

priority 16 the highest. The NMI interrupt has priority 16 and cannot be masked, so it is always

accepted. The priority level of the user break interrupt and H-UDI is 15. IRQ interrupt and on-chip

peripheral module interrupt priority levels can be set freely using the interrupt priority level setting

registers A to E (IPRA to IPRE) of the INTC as shown in table 5.8. The priority levels that can be

set are 0 to 15. Level 16 cannot be set. For details on IPRA to IPRE, see section 6.3.4, Interrupt

Priority Registers A to E (IPRA to IPRE).

Table 5.8

Interrupt Priority

Type

Priority Level

Comment

NMI

Fixed priority level. Cannot be masked.

User break

Fixed priority level. Can be masked.

H-UDI

Fixed priority level.

IRQ

0 to 15

On-chip peripheral module

Set with interrupt priority level setting registers

A through E (IPRA to IPRE).

5.4.3

Interrupt Exception Handling

When an interrupt occurs, the interrupt controller (INTC) ascertains its priority level. NMI is

always accepted, but other interrupts are only accepted if they have a priority level higher than the

priority level set in the interrupt mask bits (I3 to I0) of the status register (SR).

When an interrupt is accepted, exception handling begins. In interrupt exception handling, the

CPU saves SR and the program counter (PC) to the stack. The priority level of the accepted

interrupt is written to bits I3 to I0 in SR. Although the priority level of the NMI is 16, the value set

in bits I3 to I0 is H'F (level 15). Next, the start address of the exception handling routine is fetched

from the exception handling vector table for the accepted interrupt, and program execution

branches to that address and the program starts. For details on the interrupt exception handling, see

section 6.6, Interrupt Operation.

HD6417618A Datasheet(PDF) 105 Page - Renesas Technology Corp

HD6417618A Datasheet(HTML) 105 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL