AS7150 datasheet(146/159 Pages) AMSOSRAM

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AS7150

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DS001130 • v3-00 • 2026-Jan-26

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8.15.4

FIFO_LEVEL1 register (Address 0xFC)

Table 141: FIFO_LEVEL1 register

Addr: 0xFC

FIFO_LEVEL1

Bit

Bit name

Default

Access

Bit description

fifo_overflow

This is the FIFO overflow status bit.

0: No FIFO overflow

1: FIFO overflow

1:0

fifo_level[9:8]

This is the upper 2- bit FIFO level register.

8.15.5

FIFOL register (Address 0xFD)

The FIFO can be read with individual read accesses (three consecutive I²C addresses for a

FIFO entry) or with burst read accesses (n * 3 bytes for n FIFO entry). By reading FIFOL, a

FIFO entry is read from the FIFO and the FIFO level is reduced. If you read beyond the end of

the FIFO, the last FIFO entry will be repeated. There is no underflow flag; this is not an error

condition. The FIFO level is 512 entries.

Table 142: FIFOL register

Addr: 0xFD

FIFOL

Bit

Bit name

Default

Access

Bit description

7:4

PUSHPOP

These are the lower 4 bits of the ADC data

reading.

fifol

PUSHPOP

This bit contains the block frame information.

2:0

PUSHPOP

This bit contains the data marker information.

Please refer to Figure 32 for more information

regarding the data marker.

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