AS7150 datasheet(97/159 Pages) AMSOSRAM

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AS7150

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DS001130 • v3-00 • 2026-Jan-26

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8.9.2

SEQ_SUB_WAIT register (Address 0x41)

Table 60: SEQ_SUB_WAIT register

Addr: 0x41

SEQ_SUB_WAIT

Bit

Bit name

Default

Access

Bit description

7:0

sub_wait

R/W

This register controls the subsample wait

time tSUB_WAIT which can be added to have

breaks in between each subsample. A

detailed timing diagram which shows

tSUB_WAIT can be found in chapter 7.6.5. The

waiting time is a multiple of 1 µs of the

0 – 255µs as subsample waiting time.

8.9.3

SEQ_MODCONF register (Address 0x42)

Table 61: SEQ_MODCONF register

Addr: 0x42

SEQ_MODCONF

Bit

Bit name

Default

Access

Bit description

4:2

mod_reset_delay

R/W

This register configures the ADC modulator

settling time tMOD_RES after startup or standby

mode start of the modulators. A detailed

timing diagram which shows tMOD_RES can be

found in chapter 7.6.5. The reset times for

the different register settings which are

shown below are calculated for fMOD_CLK of 10

MHz which is configured via register modclk.

0: 4 * (1/ fMOD_CLK) = 0.4 µs

1: 8 * (1/ fMOD_CLK) = 0.8 µs

2: 16 * (1/ fMOD_CLK) = 1.6 µs

3: 32 * (1/ fMOD_CLK) = 3.2 µs

4: 64 * (1/ fMOD_CLK) = 6.4 µs

5: 128 * (1/ fMOD_CLK) = 12.8 µs

6: 256 * (1/ fMOD_CLK) = 25.6 µs

7: 256 * (1/ fMOD_CLK) = 25.6 µs

1:0

modclk

R/W

This register controls the ADC modulator

clock frequency fMOD_CLK which is used for

both sequencers and ADC modulators.

0: 10MHz

1: 5MHz

2: 2.5MHz

3: 1.25MHz

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