AS7150 datasheet(145/159 Pages) AMSOSRAM

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AS7150

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DS001130 • v3-00 • 2026-Jan-26

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8.15.2

FIFO_CTRL register (Address 0xD1)

Table 139: FIFO_CTRL register

Addr: 0xD1

FIFO_CTRL

Bit

Bit name

Default

Access

Bit description

fifo_clear

PUSH

This self-clearing bit deletes the FIFO on chip

memory.

sar_data_en

R/W

In order to reduce I²C traffic, especially when

high sample rates are used in the system, this bit

allows to copy the 4-bit SAR data to the least

significant bits of the ADC data stream. This

means from the 20 transferred ADC data bits the

bits 0 to 3 are overwritten with SAR data. With

this feature you avoid reading an additional data

word to get the SAR information.

0: SAR copy function to ADC data stream

disabled.

1: SAR copy function to ADC data stream

enabled

fifo_threshold[8]

R/W

This is MSB of the 9-bit FIFO threshold register.

8.15.3

FIFO_LEVEL0 register (Address 0xFB)

Table 140: FIFO_LEVEL0 register

Addr: 0xFB

FIFO_LEVEL0

Bit

Bit name

Default

Access

Bit description

7:0

fifo_level[7:0]

This is the lower 8-bit FIFO level register.

AS7150 Datasheet(PDF) 145 Page - ams-OSRAM AG

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