AS7150 datasheet(141/159 Pages) AMSOSRAM

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AS7150

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DS001130 • v3-00 • 2026-Jan-26

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8.14.2

STANDBY_EN1 register (Address 0xA1)

Table 131: STANDBY_EN1 register

Addr: 0xA1

STANDBY_EN1

Bit

Bit name

Default

Access

Bit description

7:0

stby_en1_time

R/W

This register controls the standby timing for

Standby Enable 1 block. Please refer to

Figure 41 for a detailed timing diagram of

tSTANDBY_1. The standby wait time tSTANDBY_1 is

calculated with the following formula:

��_1_�� = ��_��1_�� ∗ 31.25 µ��

The timing diagram shown in Figure 41 shows

that the Standby Enable 1 block controls also the

PLL block which has one clock cycle delay to the

oscillator block resulting in the following formula

for the PLL start block:

��_1_�� = (��_��1_�� + 1) ∗ 31.25 µ��

8.14.3

STANDBY_EN2 register (Address 0xA2)

Table 132: STANDBY_EN2 register

Addr: 0xA2

STANDBY_EN2

Bit

Bit name

Default

Access

Bit description

7:0

stby_en2_time

R/W

This register controls the standby timing for

Standby Enable 2 block. Please refer to

Figure 41 for a detailed timing diagram of

tSTANDBY_2. The standby wait time tSTANDBY_2 is

calculated with the following formula:

��_2 = ��_��2_�� ∗ 31.25 µ��

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