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STM32L4P5CE Datasheet(PDF) 156 Page - STMicroelectronics |
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STM32L4P5CE Datasheet(HTML) 156 Page - STMicroelectronics |
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156 / 311 page ![]() Table 36. Typical current consumption in Run and Low-power run modes, with different codes running from Flash, ART enable (Cache ON Prefetch OFF) and power supplied by external SMPS Symbol Parameter Conditions(1) TYP Single Bank Mode TYP Dual Bank Mode Unit TYP Single Bank Mode TYP Dual Bank Mode Unit - VDD12 fHCLK Code 25°C 25°C 25°C 25°C IDD (Run) Supply current in Run mode fHCLK=fHSE up to 48 MHZ included, bypass mode PLL ON above 48 MHz all peripherals disable VDD12=1.00V fHCLK= 26 MHz Reduced code 1.18 1.24 mA 45 48 µA/MHz Coremark 1.28 1.31 49 51 Dhrystone2.1 1.43 1.39 55 53 Fibonacci 1.29 1.37 50 53 While(1) 1.09 1.09 42 42 VDD12=1.10V fHCLK= 26 MHz Reduced code 1.43 1.5 mA 55 58 µA/MHz Coremark 1.54 1.59 59 61 Dhrystone2.1 1.73 1.68 66 65 Fibonacci 1.57 1.66 60 64 While(1) 1.32 1.32 51 51 fHCLK= 80 MHz Reduced code 3.95 4.13 mA 49 52 µA/MHz Coremark 4.49 4.67 56 58 Dhrystone2.1 4.85 4.67 61 58 Fibonacci 4.49 4.67 56 58 While(1) 3.77 3.77 47 47 |
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