STM32L4P5CE datasheet(43/311 Pages) STMICROELECTRONICS

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DS12903 Rev 2

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STM32L4P5xx

Functional overview

3.14

DMA request router (DMAMux)

When a peripheral indicates a request for DMA transfer by setting its DMA request line, the

DMA request is pending until it is served and the corresponding DMA request line is reset.

The DMA request router allows to route the DMA control lines between the peripherals and

the DMA controllers of the product.

An embedded multi-channel DMA request generator can be considered as one of such

peripherals. The routing function is ensured by a multi-channel DMA request line

multiplexer. Each channel selects a unique set of DMA control lines, unconditionally or

synchronously with events on synchronization inputs.

For simplicity, the functional description is limited to DMA request lines. The other DMA

control lines are not shown in figures or described in the text. The DMA request generator

produces DMA requests following events on DMA request trigger inputs.

3.15

Chrom-ART Accelerator (DMA2D)

Chrom-ART Accelerator (DMA2D) is a graphic accelerator that offers an advanced bit

blitting, row data copy and pixel format conversion. It supports the following functions:

•

Rectangle filling with a fixed color

•

Rectangle copy

•

Rectangle copy with pixel format conversion

•

Rectangle composition with blending and pixel format conversion.

Various image format coding are supported, from indirect 4 bpp color mode up to 32 bpp

direct color. It embeds a dedicated memory to store color lookup tables.

An interrupt can be generated when an operation is complete or at a programmed

watermark.

All the operations are fully automatized and are running independently from the CPU or the

DMAs.

3.16

Interrupts and events

3.16.1

Nested vectored interrupt controller (NVIC)

The STM32L4P5xx devices embed a nested vectored interrupt controller which is able to

manage 16 priority levels, and to handle up to 95 maskable interrupt channels plus the 16

interrupt lines of the Cortex®-M4.

The NVIC benefits are the following:

•

Closely coupled NVIC gives low latency interrupt processing

•

Interrupt entry vector table address passed directly to the core

•

Allows early processing of interrupts

•

Processing of late arriving higher priority interrupts

•

Support for tail chaining

•

Processor state automatically saved

•

Interrupt entry restored on interrupt exit with no instruction overhead

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