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STM32L4P5CE Datasheet(PDF) 63 Page - STMicroelectronics |
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STM32L4P5CE Datasheet(HTML) 63 Page - STMicroelectronics |
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63 / 311 page  DS12903 Rev 2 63/311 STM32L4P5xx Functional overview 64 3.42 Universal serial bus on-the-go full-speed (OTG_FS) The devices embed an USB OTG full-speed device/host/OTG peripheral with integrated transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and with the OTG 2.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG controller requires a dedicated 48 MHz clock that can be provided by the internal multispeed oscillator (MSI) automatically trimmed by 32.768 kHz external oscillator (LSE).This allows to use the USB device without external high speed crystal (HSE). The major features are: • Combined Rx and Tx FIFO size of 1.25 Kbytes with dynamic FIFO sizing • Supports the session request protocol (SRP) and host negotiation protocol (HNP) • One bidirectional control endpoint + 5 IN endpoints + 5 OUT endpoints • Eight host channels with periodic OUT support • HNP/SNP/IP inside (no need for any external resistor) • Software configurable to OTG 1.3 and OTG 2.0 modes of operation • OTG 2.0 Supports ADP (Attach detection Protocol) • USB 2.0 LPM (Link Power Management) support • Battery charging specification revision 1.2 support • Internal FS OTG PHY support For OTG/Host modes, a power switch is needed in case bus-powered devices are connected. The synchronization for this oscillator can also be taken from the USB data stream itself (SOF signalization) which allows crystal less operation. 3.43 Development support 3.43.1 Serial wire JTAG debug port (SWJ-DP) The Arm® SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. Debug is performed using two pins only instead of five required by the JTAG (JTAG pins could be re-used as GPIO with alternate function): the JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. |
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