STM32L4P5CE datasheet(44/311 Pages) STMICROELECTRONICS

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Functional overview

STM32L4P5xx

44/311

DS12903 Rev 2

The NVIC hardware block provides flexible interrupt management features with minimal

interrupt latency.

3.16.2

Extended interrupt/event controller (EXTI)

The extended interrupt/event controller consists of 36 edge detector lines used to generate

interrupt/event requests and to wake up the system from the Stop mode. Each external line

can be independently configured to select the trigger event (rising edge, falling edge, both)

and can be masked independently.

A pending register maintains the status of the interrupt requests. The internal lines are

connected to peripherals with wakeup from Stop mode capability. The EXTI can detect an

external line with a pulse width shorter than the internal clock period. Up to 114 GPIOs can

be connected to the 16 external interrupt lines.

3.17

Cyclic redundancy check calculation unit (CRC)

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a

configurable generator with polynomial value and size.

Among other applications, the CRC-based techniques are used to verify data transmission

or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a mean to verify

the Flash memory integrity.

The CRC calculation unit helps to compute a signature of the software during runtime, which

can be ulteriorly compared with a reference signature generated at link-time and which can

be stored at a given memory location.

3.18

Flexible static memory controller (FSMC)

The flexible static memory controller (FSMC) includes two memory controllers:

•

The NOR/PSRAM memory controller

•

The NAND/memory controller

This memory controller is also named flexible memory controller (FMC).

The main features of the FSMC controller are the following:

•

Interface with static-memory mapped devices including:

–

Static random access memory (SRAM)

–

NOR Flash memory/OneNAND Flash memory

–

PSRAM (four memory banks)

–

NAND Flash memory with ECC hardware to check up to 8 Kbytes of data

–

Ferroelectric RAM (FRAM)

•

8-,16- bit data bus width

•

Independent chip select control for each memory bank

•

Independent configuration for each memory bank

•

Write FIFO

•

The Maximum FMC_CLK frequency for synchronous accesses is HCLK/2.

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