STM32L4P5CE datasheet(35/311 Pages) STMICROELECTRONICS

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DS12903 Rev 2

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STM32L4P5xx

Functional overview

3.7.5

Reset mode

In order to improve the consumption under reset, the I/Os state under and after reset is

“analog state” (the I/O schmitt trigger is disable). In addition, the internal reset pull-up is

deactivated when the reset source is internal.

3.7.6

VBAT operation

The VBAT pin allows the device VBAT domain to be powered from an external battery, an

external supercapacitor, or from VDD when there is no external battery and when an external

supercapacitor is present. The VBAT pin supplies the RTC with LSE and the backup

registers. Three anti-tamper detection pins are available in VBAT mode.

The VBAT operation is automatically activated when VDD is not present. An internal VBAT

battery charging circuit is embedded and can be activated when VDD is present.

Note:

When the microcontroller is supplied from VBAT, neither external interrupts nor RTC

alarm/events exit the microcontroller from the VBAT operation.

3.8

Peripheral and interconnect matrix

Several peripherals have direct connections between them, which allow autonomous

communication between them and support the saving of CPU resources (thus power supply

consumption). In addition, these hardware connections allow fast and predictable latency.

Depending on the peripherals, these interconnections can operate in Run, Sleep, Low-

power run, Low-power Sleep, Stop 0, Stop 1 and Stop 2 modes. See Table 6 for more

details.

Table 6. STM32L4P5xx peripherals interconnect matrix

Interconnect source

Interconnect

destination

Interconnect action

TIMx

Timers synchronization or chaining

ADCx

DAC1

DFSDM1

Conversion triggers

DMA

Memory to memory transfer trigger

COMPx

Comparator output blanking

COMPx

TIM1, 8

TIM2, 3

Timer input channel, trigger, break from

analog signals comparison

LPTIMERx

Low-power timer triggered by analog

signals comparison

ADCx

TIM1, 8

Timer triggered by analog watchdog

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