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STM32L4P5CE Datasheet(PDF) 38 Page - STMicroelectronics |
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STM32L4P5CE Datasheet(HTML) 38 Page - STMicroelectronics |
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38 / 311 page ![]() Functional overview STM32L4P5xx 38/311 DS12903 Rev 2 interrupt is generated if enabled. LSE failure can also be detected and generated an interrupt. • Clock-out capability: – MCO (microcontroller clock output): it outputs one of the internal clocks for external use by the application – LSCO (low-speed clock output): it outputs LSI or LSE in all low-power modes (except VBAT). Several prescalers allow the AHB frequency, the high speed APB (APB2) and the low- speed APB (APB1) domains to be configured. The maximum frequency of the AHB and the APB domains is 120 MHz. |
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