PIC24FJ64GA310 datasheet(93/406 Pages) MICROCHIP

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DS39996F-page 93

PIC24FJ128GA310 FAMILY

TABLE 7-1:

RESET FLAG BIT OPERATION

7.1

Special Function Register Reset

States

Most of the Special Function Registers (SFRs) associ-

ated with the PIC24F CPU and peripherals are reset to a

particular value at a device Reset. The SFRs are

grouped by their peripheral or CPU function and their

Reset values are specified in each section of this manual.

The Reset value for each SFR does not depend on the

type of Reset, with the exception of four registers. The

Reset value for the Reset Control register, RCON, will

depend on the type of device Reset. The Reset value

for the Oscillator Control register, OSCCON, will

depend on the type of Reset and the programmed

values of the FNOSC bits in Flash Configuration

Word 2 (CW2) (see Table 7-2). The RCFGCAL and

NVMCON registers are only affected by a POR.

7.2

Device Reset Times

The Reset times for various types of device Reset are

summarized in Table 7-3. Note that the system Reset

signal, SYSRST, is released after the POR delay time

expires.

The time at which the device actually begins to execute

code will also depend on the system oscillator delays,

which include the Oscillator Start-up Timer (OST) and

the PLL lock time. The OST and PLL lock times occur

in parallel with the applicable SYSRST delay times.

The Fail-Safe Clock Monitor (FSCM) delay determines

the time at which the FSCM begins to monitor the

system clock source after the SYSRST signal is

released.

7.3

Brown-out Reset (BOR)

PIC24FJ128GA310 family devices implement a BOR

circuit that provides the user with several configuration

and power-saving options. The BOR is controlled by

the BOREN (CW3<12>) Configuration bit.

When BOR is enabled, any drop of VDD below the BOR

threshold results in a device BOR. Threshold levels are

described in Section 32.1 “DC Characteristics”

(Parameter DC17).

7.4

Clock Source Selection at Reset

If clock switching is enabled, the system clock source

at device Reset is chosen, as shown in Table 7-2. If

clock switching is disabled, the system clock source is

always selected according to the Oscillator Configura-

tion bits. Refer to the “PIC24F Family Reference

Manual

”, Section 6.0 “Oscillator” (DS39700) for

further details.

TABLE 7-2:

OSCILLATOR SELECTION vs.

TYPE OF RESET (CLOCK

SWITCHING ENABLED)

Flag Bit

Setting Event

Clearing Event

TRAPR (RCON<15>)

Trap Conflict Event

POR

IOPUWR (RCON<14>)

Illegal Opcode or Uninitialized W Register Access

POR

CM (RCON<9>)

Configuration Mismatch Reset

POR

EXTR (RCON<7>)

MCLR Reset

POR

SWR (RCON<6>)

RESET

Instruction

POR

WDTO (RCON<4>)

WDT Time-out

CLRWDT, PWRSAV

Instruction, POR

SLEEP (RCON<3>)

PWRSAV #0

Instruction

POR

DPSLP (RCON<10>)

PWRSAV #0

Instruction while DSEN bit set

POR

IDLE (RCON<2>)

PWRSAV #1

Instruction

POR

BOR (RCON<1>)

POR, BOR

—

POR (RCON<0>)

POR

—

Note:

All Reset flag bits may be set or cleared by the user software.

Reset Type

Clock Source Determinant

POR

FNOSC Configuration bits

(CW2<10:8>)

BOR

MCLR

COSC Control bits

(OSCCON<14:12>)

WDTO

SWR

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