PIC24FJ64GA310 datasheet(89/406 Pages) MICROCHIP

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 2010-2011 Microchip Technology Inc.

DS39996F-page 89

PIC24FJ128GA310 FAMILY

7.0

RESETS

The Reset module combines all Reset sources and

controls the device Master Reset Signal, SYSRST. The

following is a list of device Reset sources:

• POR: Power-on Reset

•MCLR: Pin Reset

•SWR: RESET Instruction

• WDT: Watchdog Timer Reset

• BOR: Brown-out Reset

• CM: Configuration Mismatch Reset

• TRAPR: Trap Conflict Reset

• IOPUWR: Illegal Opcode Reset

• UWR: Uninitialized W Register Reset

A simplified block diagram of the Reset module is

shown in Figure 7-1.

Any active source of Reset will make the SYSRST

signal active. Many registers associated with the CPU

and peripherals are forced to a known Reset state.

Most registers are unaffected by a Reset; their status is

unknown on POR and unchanged by all other Resets.

All types of device Reset will set a corresponding status

bit in the RCON register to indicate the type of Reset

(see Register 7-1). In addition, Reset events occurring

while an extreme power-saving feature is in use (such

as VBAT) will set one or more status bits in the RCON2

for the BOR and POR (RCON<1:0>) bits, which are

set. The user may set or clear any bit at any time during

code execution. The RCON bits only serve as status

bits. Setting a particular Reset status bit in software will

not cause a device Reset to occur.

The RCON register also has other bits associated with

the Watchdog Timer and device power-saving states.

The function of these bits is discussed in other sections

of this data sheet.

FIGURE 7-1:

RESET SYSTEM BLOCK DIAGRAM

Note:

This data sheet summarizes the features of

this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. For more information, refer to the

“PIC24F

Family

Reference

Manual

”,

Section 7. “Reset”

(DS39712). The infor-

mation in this data sheet supersedes the

information in the FRM.

Note:

Refer to the specific peripheral or CPU

section of this manual for register Reset

states.

Note:

The status bits in the RCON registers

should be cleared after they are read so

that the next RCON register values after a

device Reset will be meaningful.

MCLR

VDD

VDD Rise

Detect

POR

Sleep or Idle

Brown-out

Reset

Enable Voltage Regulator

RESET

Instruction

WDT

Module

Glitch Filter

BOR

Trap Conflict

Illegal Opcode

Uninitialized W Register

SYSRST

Configuration Mismatch

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