PIC24FJ64GA310 datasheet(42/406 Pages) MICROCHIP

42 / 406 page

PIC24FJ128GA310 FAMILY

DS39996F-page 42

 2010-2011 Microchip Technology Inc.

4.1.1

PROGRAM MEMORY

ORGANIZATION

The program memory space is organized in

word-addressable blocks. Although it is treated as

24 bits wide, it is more appropriate to think of each

address of the program memory as a lower and upper

word, with the upper byte of the upper word being

unimplemented. The lower word always has an even

address, while the upper word has an odd address

(Figure 4-2).

Program memory addresses are always word-aligned

on the lower word and addresses are incremented or

decremented by two during code execution. This

arrangement also provides compatibility with data

memory space addressing and makes it possible to

access data in the program memory space.

4.1.2

HARD MEMORY VECTORS

All PIC24F devices reserve the addresses between

000000h and 000200h for hard-coded program execu-

tion vectors. A hardware Reset vector is provided to

redirect code execution from the default value of the

PC on device Reset to the actual start of code. A GOTO

instruction is programmed by the user at 000000h with

the actual address for the start of code at 000002h.

PIC24F devices also have two interrupt vector tables,

located from 000004h to 0000FFh and 000100h to

0001FFh. These vector tables allow each of the many

device interrupt sources to be handled by separate

ISRs. A more detailed discussion of the interrupt vector

tables is provided in Section 8.1 “Interrupt Vector

Table”

4.1.3

FLASH CONFIGURATION WORDS

In PIC24FJ128GA310 family devices, the top four words

of on-chip program memory are reserved for configura-

tion information. On device Reset, the configuration

information is copied into the appropriate Configuration

for devices in the PIC24FJ128GA310 family are shown

in Table 4-1. Their location in the memory map is shown

with the other memory vectors in Figure 4-1.

The Configuration Words in program memory are a

compact format. The actual Configuration bits are

mapped in several different registers in the configuration

memory space. Their order in the Flash Configuration

Words does not reflect a corresponding arrangement in

the configuration space. Additional details on the device

Configuration Words are provided in Section 29.0

“Special Features”

TABLE 4-1:

FLASH CONFIGURATION

WORDS FOR

PIC24FJ128GA310 FAMILY

DEVICES

FIGURE 4-2:

PROGRAM MEMORY ORGANIZATION

Device

Program

Memory

(Words)

Configuration Word

Addresses

PIC24FJ64GA3XX

22,016

00ABF8h:00ABFEh

PIC24FJ128GA3XX

44,032

0157F8h:0157FEh

PC Address

0x000000

0x000002

0x000004

0x000006

00000000

Program Memory

‘Phantom’ Byte

(read as ‘0’)

least significant word

most significant word

Instruction Width

0x000001

0x000003

0x000005

0x000007

msw

Address

(lsw Address)

PIC24FJ64GA310 Datasheet(PDF) 42 Page - Microchip Technology

PIC24FJ64GA310 Datasheet(HTML) 42 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL