PIC24FJ64GA310 datasheet(64/406 Pages) MICROCHIP

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TABLE 4-32:

DEEP SLEEP REGISTER MAP

File Name

Addr

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

All

Resets

DSCON

0758

DSEN

—

DSBOR

RELEASE 0000(1)

DSWAKE

075A

—

DSINT0

DSFLT

—

DSWDT DSRTCC DSMCLR

—

0000(1)

DSGPR0

075C

Deep Sleep Semaphore Data 0

0000(1)

DSGPR1

075E

Deep Sleep Semaphore Data 1

0000(1)

Legend:

— = unimplemented, read as ‘0’; r = reserved. Reset values are shown in hexadecimal.

Note 1:

These registers are only reset on a VDD POR event.

TABLE 4-33:

NVM REGISTER MAP

File Name

Addr

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

All

Resets

NVMCON

0760

WREN

WRERR

—

—ERASE

—

NVMOP3 NVMOP2 NVMOP1 NVMOP0 0000(1)

NVMKEY

0766

—

NVMKEY Register<7:0>

0000

Legend:

— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1:

The Reset value shown is for POR only. The value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset.

TABLE 4-34:

PMD REGISTER MAP

File Name

Addr

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

All

Resets

PMD1

0770

T5MD

T4MD

T3MD

T2MD

T1MD

—

I2C1MD

U2MD

U1MD

SPI2MD

SPI1MD

—

ADC1MD

0000

PMD2

0772

—

IC7MD

IC6MD

IC5MD

IC4MD

IC3MD

IC2MD

IC1MD

—

OC7MD

OC6MD

OC5MD

OC4MD

OC3MD

OC2MD

OC1MD

0000

PMD3

0774

—

DSMMD

CMPMD RTCCMD

PMPMD

CRCMD

—

—U3MD

—I2C2MD

—

0000

PMD4

0776

—

—UPWMMD

U4MD

—

REFOMD CTMUMD

LVDMD

—

0000

PMD6

077A

—

LCDMD

—

—SPI3MD

0000

PMD7

077C

—

DMA1MD DMA0MD

—

0000

Legend:

— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

PIC24FJ64GA310 Datasheet(PDF) 64 Page - Microchip Technology

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