TNETX3100 datasheet(11/80 Pages) TI1

11 / 80 page

TNETX3100

ThunderSWITCH™ 10-PORT 10-/100-MBIT/S ETHERNET™ SWITCH

SPWS031D – JUNE 1997 – REVISED OCTOBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

Terminal Functions (Continued)

EEPROM interface

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

ECLK

153

EEPROM data clock. ECLK is the serial EEPROM clock and requires an external pullup resistor.

EDIO

152

I/O

EEPROM data input/output. EDIO is the serial EEPROM data I/O signal that requires an external pullup (see

EEPROM data sheet) for EEPROM operation. Tying this terminal to ground disables the EEPROM interface

and prevents auto-configuration. Reset is asynchronous, therefore, OSCIN needs to operate while RESET

is active.

LED activity interface

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

LEDCLK

129

LED clock. LEDCLK is the serial-shift clock for the LED-status data.

LEDDATA

128

LED data. LEDDATA is the active-low serial data signal for the LED-status data.

LEDSTR

124

LED strobe. LEDSTR pulses latch the contents of the LED shift registers.

JTAG interface

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

TCLK

148

Test clock. TCLK clocks state information and test data into and out of the device during operation of the

test port.

TDI

149

Test data input. TDI serially shifts test data and test instructions into the device during operation of the test

port.

TDO

150

Test data out. TDO serially shifts test data and test instructions out of the device during operation of the test

port.

TMS

151

Test mode select. TMS controls the state of the TNETX3100 test-port controller.

TRST

147

Test reset. TRST asynchronously resets the test-port controller.

miscellaneous functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

DREF

125

DRAM reference clock.

OSCIN

127

Oscillator input. OSCIN is the TNETX3100 clock input (50 MHz).

RESET

146

Reset. RESET (active low) resets the TNETX3100. RESET should be held low for 25 ms after the power

supplies and clocks have stabilized. This input is synchronous and therefore, the system clock is operational

during reset.

TNETX3100 Datasheet(PDF) 11 Page - Texas Instruments

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